A silicon carbide (hereinafter also referred to as “SiC”) semiconductor substrate having a large bandgap width has attracted attention as a substrate of a semiconductor device for high voltage applications. FIG. 18 shows a cross-sectional structure of a MOSFET (100) having a general vertical structure formed of SiC. An active layer 120 is formed on an element support substrate 110 by epitaxial growth, and a source 101, a drain 102, and a gate 103 are formed in a region of the active layer 120. Conduction and cutoff of current between the source 101 and the drain 102 is controlled by the gate 103. A drain current i at the time of conduction flows between the drain 102 and a drain electrode 104 formed on a bottom surface of the element support substrate 110.
The element support substrate 110 is a region in which current flows in the vertical direction (up/down direction in the drawing) and has a low resistivity of 20 mΩ·cm or less. On the other hand, since the active layer 120 needs to withstand a high voltage, the active layer 120 has a resistivity higher by 2 to 3 digits than that of the element support substrate 110. Since a semiconductor device using SiC has a large bandgap width, it is characterized in that the thickness of the active layer 120 can be reduced to approximately 5 to 10 μm. The thickness of the element support substrate 110 is set to approximately 300 μm in the case of a 6-inch substrate in order to, for example, prevent cracking during handling of a single crystal substrate. Since the active layer 120 is formed by epitaxial growth on the element support substrate 110, its crystallinity depends on the element support substrate 110 which becomes a base. Thus, the crystal quality of SiC of the element support substrate 110 is important.
Since SiC is a compound consisting of carbon and silicon having different lattice constants, many crystal defects occur in an element substrate. Particularly, in power device applications, crystal defects are fatal, and therefore, various attempts have been made to reduce the crystal defects; however, the cost of the element substrate is accordingly increased. For this reason, it is aimed to simultaneously achieve crystal defect reduction and cost reduction of the element support substrate 110 which is a base of the active layer 120 to be epitaxially grown. In the case of the vertical structure as shown in FIG. 18, in order to flow current in the vertical direction, the element support substrate 110 needs to have a low resistivity, and therefore, high concentration nitrogen is added to provide an N-type semiconductor. However, there is a problem that crystal defects are further increased due to the high concentration nitrogen.
In order to reduce crystal defects and reduce costs, there has been known a method of bonding a single crystal layer having good crystallinity on a low cost polycrystalline substrate. For example, there is a substrate manufacturing method in which amorphous silicon is vapor-deposited on a polycrystalline SiC support, and the polycrystalline SiC support and a single crystal SiC substrate are bonded and integrated by direct bonding (refer to Patent Literature 1). There is also an example in which substrates are bonded together by a surface activation method using a FAB gun (Fast Atomic Gun) (refer to Non-Patent Literature 1). Further, in order to bond two semiconductor layers together, there is a method in which the surface of each semiconductor layer is irradiated with an inactive impurity such as argon to be temporarily made amorphous, and thus to be recrystallized by heat treatment after bonding the two semiconductor layers. By this method, it has been confirmed that there is continuity at the atomic level at two bonded interfaces (refer to Non Patent Literatures 1 and 2).
From these findings, it is also conceivable to form an inexpensive and highly crystalline substrate by bonding an inexpensive polycrystalline substrate irrespective of crystallinity and a single crystal substrate having good crystallinity.
However, since such a substrate has a bonding interface, if there is a partial bonding defect, this causes lowering of the yield of the element. In order to achieve defect-free bonding, if polishing is performed to increase flatness of surfaces of both substrates, there is a problem that the polishing cost becomes expensive. In addition, it is difficult to eliminate entrainment of particles caused by, for example, a bonding apparatus or various atomic components present at the bonding interface. The greatest problem of the method of forming the element substrate by bonding is that the bonding interface exists in a final semiconductor substrate.
In order to solve the above problem, a method for manufacturing a semiconductor substrate which, as a finished product, does not have a bonding interface has been proposed (refer to Patent Literature 2).